使用VHDL语言实现TXT文件的读写操作

使用FPGA进行图像处理时，通常需要将TXT文件中的图像数据读出到TestBench中，并将仿真的结果写入到TXT文件中，用于确认图像处理的结果是否正确。

VHDL中TXT文件的读写操作如下所示，

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 2025/04/18 21:34:38
-- Design Name: 
-- Module Name: tb_txt_rdwr - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;-- testio程序包是std库的一部分


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tb_txt_rdwr is
--  Port ( );
end tb_txt_rdwr;

architecture Behavioral of tb_txt_rdwr is

constant clk_period : time := 10 ns; 

signal clk : std_logic;
signal rst : std_logic;

signal wrdata : std_logic_vector(3 downto 0);
signal wren : std_logic;
signal wrdone : std_logic;

signal rddata : std_logic_vector(3 downto 0);
signal rden : std_logic;
signal rddone : std_logic;

begin

-----------------------------------
--生成时钟复位信号
process
begin
    clk <= '0'; 
    wait for clk_period/2;
    clk <= '1'; 
    wait for clk_period/2;
end process;

process
begin
    rst <= '1';
    wait for clk_period*200;
    rst <= '0';
    wait ;
end process;

-----------------------------------
--生成要写入TXT文件中的二进制数据
process
begin
    wrdata <= (others=>'0');
    wren <= '0';
    wrdone <= '0';
    wait until falling_edge(rst);

    wait until rising_edge(clk);
    wait until rising_edge(clk);
    wait until rising_edge(clk);
    
    for i in 15 downto 0 loop   
        wren <= '1';
        wait until rising_edge(clk);
        wrdata <= wrdata + x"1";
    end loop;
    wren <= '0';  

    wait until rising_edge(clk);
    wait until rising_edge(clk);
    wait until rising_edge(clk);  
    wrdone <= '1';
    wait until rising_edge(clk);
    wrdone <= '0';
    wait ;
end process;

-----------------------------------
--写数据到TXT文件中
process(clk,rst)
    file v_file : text;
    variable v_line : line;
    variable v_data : std_logic_vector(3 downto 0);
begin
    if rst='1' then
        file_open(v_file,"E:\forsim\txt_from_vhdl_tb.txt",write_mode);
    elsif rising_edge(clk) then
        if wren='1' then
            v_data := wrdata;
            write(v_line,v_data);
            writeline(v_file,v_line);
        elsif wrdone='1' then
            file_close(v_file);
        end if;
    end if;
end process;

-----------------------------------
--生成TXT文件的读使能信号和读结束信号
process
begin
    rden <= '0';
    rddone <= '0';
    wait until falling_edge(wrdone); --检测到TXT文件写操作结束后，从TXT文件中读出写入的数据

    wait until rising_edge(clk);
    wait until rising_edge(clk);
    wait until rising_edge(clk);
    
    for i in 15 downto 0 loop   
        rden <= '1';
        wait until rising_edge(clk);
    end loop;
    rden <= '0';

    wait until rising_edge(clk);
    wait until rising_edge(clk);
    wait until rising_edge(clk);
    rddone <= '1';
    wait until rising_edge(clk);
    rddone <= '0';
    wait ;
end process;

-----------------------------------
--从TXT文件中读出数据，并赋值到rdtata
process(clk,rst)
    file v_file : text;
    variable v_line : line;
    variable v_data : std_logic_vector(3 downto 0);
begin
    if rst='1' then
        file_open(v_file,"E:\forsim\txt_from_vhdl_tb.txt",read_mode);
        rddata <= (others=>'0');
    elsif rising_edge(clk) then
        if rden='1' then
            readline(v_file,v_line);
            read(v_line,v_data);
            rddata <= v_data;
        elsif rddone='1' then
            file_close(v_file);
        end if;
    end if;
end process;

end Behavioral;