ARMV8 RK3399 u-boot TPL启动流程分析 --start.S

上电后运行的第一支文件：arch/arm/cpu/armv8/start.S

CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=1

#include <asm/arch/boot0.h>

跳转到 arch/arm/include/asm/arch-rockchip/boot0.h

CONFIG_SPL_BUILD=1

b 1f

ROCKCHIP_EARLYRETURN_TO_BROM=no

TINY_FRAMEWORK=no

b reset

reset 位于 arch/arm/cpu/armv8/start.S

b save_boot_params

save_boot_params 位于arch/arm/mach-rockchip/bootrom.c

Rockchip BROM 有设置stackpointer, 此处可以正常运行c code

1. ret = setjmp(brom_ctx);

setjmp 位于arch/arm/lib/setjmp_aarch64.S

该函数将regs 保存到brom_ctx, 注意

a.此处需将brom_ctx强制声明为data section, bss 还未初始化，初始化时会将其清掉

b. 保存的LR等于save_boot_params的返回地址，即save_boot_params_ret

c. mov x0, #0 => ret 等于0

2. check_back_to_brom_dnl_flag

CONFIG_ROCKCHIP_BOOT_MODE_REG 0xff320300

BROM_BOOTSOURCE_ID_ADDR = no

return false

goto save_boot_params_ret

3. 设置中断向量相关，根据当前EL级别跳转到3,2,1

CONFIG_POSITION_INDEPENDENT=n

CONFIG_SYS_RESET_SCTRL=n

	adr	x0, vectors
	switch_el x1, 3f, 2f, 1f
3:	msr	vbar_el3, x0
	mrs	x0, scr_el3
	orr	x0, x0, #0xf			/* SCR_EL3.NS|IRQ|FIQ|EA */
	msr	scr_el3, x0
	msr	cptr_el3, xzr			/* Enable FP/SIMD */
#ifdef COUNTER_FREQUENCY
	ldr	x0, =COUNTER_FREQUENCY
	msr	cntfrq_el0, x0			/* Initialize CNTFRQ */
#endif
	b	0f

4 cache 相关设置

CONFIG_SYS_ICACHE_OFF=n

    mov x1, #CR_I
	switch_el x2, 3f, 2f, 1f
3:	mrs	x0, sctlr_el3
	orr	x0, x0, x1
	msr	sctlr_el3, x0
#ifndef CONFIG_SUPPORT_USBPLUG
	msr	daifclr, #4			/* Enable SError. SCR_EL3.EA=1 was already set in start.S */
#endif
	b	0f

    ...

0:
	isb

5 SMP 相关设置

CONFIG_ARMV8_SET_SMPEN=n, 跳过这段

6

/* Apply ARM core specific erratas */

bl apply_core_errata //arm 相关errata, 暂不具体分析

/* Processor specific initialization */

bl lowlevel_init  //RK3399 没有相关定义，使用start.S 中的weak function

CONFIG_IRQ=1

CONFIG_GICV3=1

7 如下都是n, 跳过分析

CONFIG_ARMV8_SPIN_TABLE=n

CONFIG_ARMV8_MULTIENTRY=n

CONFIG_ARM_SMP=n

8 

master_cpu:

bl _main //至此跳转到arch/arm/lib/crt0.S，