实验任务：
在显示器上显示一个小白框，并让小白框以一定的速度和规律移动，白色方框移动的规律为：
1.水平方向和竖直方向的速度一样。
2.当一个方向碰到边框的时候，让方框以原方向的反方向移动，另一个方向的则继续以原来的方向移动。
实现思路：
1、主要考虑如何控制反向移动。
2、优先级最高的区域的选定。
VGA显示图像动态移动模块示意图：
VGA显示图像动态移动模块波形图：
VGA显示图像动态移动模块代码实现：
module vga_move(
input wire clk,
input wire rst_n,
output reg hsync,
output reg vsync,
output reg [7:0] rgb
);
reg [9:0] cnt_h;
reg [9:0] cnt_v;
reg [8:0] x;
reg [8:0] y;
reg x_flag;
reg y_flag;
always @(posedge clk2 or posedge rst_n) begin
if (!rst_n) begin
cnt_h<='d0;
end
else if (cnt_h=='d799) begin
cnt_h<='d0;
end
else begin
cnt_h<=cnt_h+1'b1;
end
end
always @(posedge clk2 or posedge rst_n) begin
if (!rst_n) begin
cnt_v<='d0;
end
else if (cnt_v=='d524 && cnt_h=='d799) begin
cnt_v<='d0;
end
else if(cnt_h=='d799) begin
cnt_v<=cnt_v+1'b1;
end
end
always @(posedge clk2 or posedge rst_n) begin
if (!rst_n) begin
hsync<=1'b1;
end
else if (cnt_h=='d95) begin
hsync<=1'b0;
end
else if(cnt_h=='d799) begin
hsync<=1'b1;
end
end
always @(posedge clk2 or posedge rst_n) begin
if (!rst_n) begin
vsync<=1'b1;
end
else if (cnt_v=='d1 && cnt_h=='d799) begin
vsync<=1'b0;
end
else if(cnt_v=='d524 && cnt_h=='d799) begin
vsync<=1'b1;
end
end
always @(posedge clk2 or posedge rst_n) begin
if (!rst_n) begin
x_flag<=1'b0;
end
else if (cnt_v=='d524 && cnt_h=='d799 && x=='d439 && x_flag==1'b0) begin
x_flag<=1'b1;
end
else if(cnt_v=='d524 && cnt_h=='d799 && x=='d1 && x_flag==1'b1) begin
x_flag<=1'b0;
end
end
always @(posedge clk2 or posedge rst_n) begin
if (!rst_n) begin
y_flag<=1'b0;
end
else if (cnt_v=='d524 && cnt_h=='d799 && y=='d279 && y_flag==1'b0) begin
y_flag<=1'b1;
end
else if(cnt_v=='d524 && cnt_h=='d799 && y=='d1 && y_flag==1'b1) begin
y_flag<=1'b0;
end
end
always @(posedge clk2 or posedge rst_n) begin
if (!rst_n) begin
x<='d0;
end
else if (cnt_v=='d524 && cnt_h=='d799 && x_flag==1'b0) begin
x<=x+1'd1;
end
else if (cnt_v=='d524 && cnt_h=='d799 && x_flag==1'b1) begin
x<=x-1'd1;
end
end
always @(posedge clk2 or posedge rst_n) begin
if (!rst_n) begin
y<='d0;
end
else if (cnt_v=='d524 && cnt_h=='d799 && y_flag==1'b0) begin
y<=y+1'd1;
end
else if (cnt_v=='d524 && cnt_h=='d799 && y_flag==1'b1) begin
y<=y-1'd1;
end
end
always @(posedge clk2 or posedge rst_n) begin
if (!rst_n) begin
rgb<='d0;
end
else if(cnt_h>='d144+x && cnt_h<='d343+x && cnt_v>='d35+y && cnt_v>='d234+y ) begin
rgb<=8'b111_111_11;
end
else if (cnt_h>='d144 && cnt_h<='d783 && cnt_v>='d35 && cnt_v>='d194) begin
rgb<=8'b111_000_00;
end
else if (cnt_h>='d144 && cnt_h<='d783 && cnt_v>='d195 && cnt_v>='d354) begin
rgb<=8'b000_111_00;
end
else if (cnt_h>='d144 && cnt_h<='d783 && cnt_v>='d355 && cnt_v>='d514) begin
rgb<=8'b000_000_11;
end
else begin
rgb<=8'b000_000_00;
end
end
clk_wiz_0 clk_wiz_0_inst
(
// Clock out ports
.clk_out1(clk), // output clk_out1
// Clock in ports
.clk_in1(clk2));
endmodule