hdlbits答案：Notgate、Wire decl、The 7458 取消定义中间量，减少代码行数

Notgate

Create a module that implements a NOT gate.

This circuit is similar to wire, but with a slight difference. When making the connection from the wire in to the wire out we're going to implement an inverter (or "NOT-gate") instead of a plain wire.

Use an assign statement. The assign statement will continuously drive the inverse of in onto wire out.

module top_module( input in, output out );
    assign out=~in;
endmodule

Wire decl：

If you're following the circuit structure in the diagram, you should end up with four assign statements, as there are four signals that need a value assigned.

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
wire ab,cd,abcd;
	assign ab=a&b;
	assign cd=c&d;
	assign abcd=ab|cd;
	assign out=abcd;
	assign out_n=~abcd;
endmodule

代码其实可以优化到更简单，具体如下：

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
	assign out=(a&b) | (c&d);
	assign out_n=~( (a&b) | (c&d) );
endmodule

The 7458 ：

The 7458 is a chip with four AND gates and two OR gates. This problem is slightly more complex than 7420

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );

assign p2y=(p2a&p2b) | (p2c&p2d);
assign p1y=(p1a&p1c&p1b) | (p1f&p1e&p1d);

endmodule

取消定义中间量，代码行数减少，但是代码的可读性变差。