module adc128s102( input Clk, input Reset_n , input Conv_Go,//使能信号 input [2:0]Addr, output reg Conv_Done, output reg[11:0]Data, output reg ADC_SCLK, output reg ADC_CS_N, output reg ADC_DIN, input ADC_DOUT ); parameter CLOCK_FREQ = 50_000_000; parameter SCLK_FREQ = 12_500_000; parameter MCNT_DIV_CNT = CLOCK_FREQ/(SCLK_FREQ * 2) - 1; reg[7:0]DIV_CNT; reg [5:0]LSM_CNT; reg [11:0]Data_r; reg [2:0]r_Addr; always@(posedge Clk) if(Conv_Go) r_Addr <= Addr; else r_Addr <= r_Addr; reg Conv_En; //转换使能 always@(posedge Clk or negedge Reset_n ) if(!Reset_n ) Conv_En <= 1'd0; else if(Conv_Go) Conv_En <= 1'd1; else if((LSM_CNT == 6'd34) && (DIV_CNT == MCNT_DIV_CNT)) Conv_En <= 1'd0; else Conv_En <= Conv_En; always@(posedge Clk or negedge Reset_n) if(!Reset_n) DIV_CNT <= 0; else if(Conv_En)begin if(DIV_CNT == MCNT_DIV_CNT) DIV_CNT <= 0; else DIV_CNT <= DIV_CNT + 1'd1; end else DIV_CNT <= 0; always@(posedge Clk or negedge Reset_n) if(!Reset_n) LSM_CNT <= 6'd0; else if(DIV_CNT == MCNT_DIV_CNT)begin if(LSM_CNT == 6'd34) LSM_CNT <= 6'd0; else LSM_CNT <= LSM_CNT + 1'd1; end else LSM_CNT <= LSM_CNT; always@(posedge Clk or negedge Reset_n ) if(!Reset_n )begin Data_r <= 12'd0; ADC_SCLK <= 1'd1; ADC_DIN <= 1'd1; ADC_CS_N <= 1'd1; end else if(DIV_CNT == MCNT_DIV_CNT)begin case(LSM_CNT) 0 : begin ADC_CS_N <= 1'd1; ADC_SCLK <= 1'd1;end 1 : begin ADC_CS_N <= 1'd0;end 2 : begin ADC_SCLK <= 1'd0;end 3 : begin ADC_SCLK <= 1'd1;end 4 : begin ADC_SCLK <= 1'd0;end 5 : begin ADC_SCLK <= 1'd1;end 6 : begin ADC_SCLK <= 1'd0;ADC_DIN <= r_Addr[2]; end 7 : begin ADC_SCLK <= 1'd1;end 8 : begin ADC_SCLK <= 1'd0;ADC_DIN <= r_Addr[1]; end 9 : begin ADC_SCLK <= 1'd1;end 10 :begin ADC_SCLK <= 1'd0;ADC_DIN <= r_Addr[0]; end 11: begin ADC_SCLK <= 1'd1;Data_r[11] <= ADC_DOUT; end 12: begin ADC_SCLK <= 1'd0;end 13: begin ADC_SCLK <= 1'd1;Data_r[10] <= ADC_DOUT; end 14: begin ADC_SCLK <= 1'd0;end 15: begin ADC_SCLK <= 1'd1;Data_r[9] <= ADC_DOUT; end 16: begin ADC_SCLK <= 1'd0;end 17: begin ADC_SCLK <= 1'd1;Data_r[8] <= ADC_DOUT; end 18: begin ADC_SCLK <= 1'd0;end 19: begin ADC_SCLK <= 1'd1;Data_r[7] <= ADC_DOUT; end 20: begin ADC_SCLK <= 1'd0;end 21: begin ADC_SCLK <= 1'd1;Data_r[6] <= ADC_DOUT; end 22: begin ADC_SCLK <= 1'd0;end 23: begin ADC_SCLK <= 1'd1;Data_r[5] <= ADC_DOUT; end 24: begin ADC_SCLK <= 1'd0;end 25: begin ADC_SCLK <= 1'd1;Data_r[4] <= ADC_DOUT; end 26: begin ADC_SCLK <= 1'd0;end 27: begin ADC_SCLK <= 1'd1;Data_r[3] <= ADC_DOUT; end 28: begin ADC_SCLK <= 1'd0;end 29: begin ADC_SCLK <= 1'd1;Data_r[2] <= ADC_DOUT; end 30: begin ADC_SCLK <= 1'd0;end 31: begin ADC_SCLK <= 1'd1;Data_r[1] <= ADC_DOUT; end 32: begin ADC_SCLK <= 1'd0;end 33: begin ADC_SCLK <= 1'd1;Data_r[0] <= ADC_DOUT; end 34: begin ADC_SCLK <= 1'd1;ADC_CS_N <= 1'd1; end default: ADC_CS_N <= 1'd1; endcase end always@(posedge Clk or negedge Reset_n ) if(!Reset_n )begin Data <= 12'd0; Conv_Done <= 0; end else if((LSM_CNT == 34) && (DIV_CNT == MCNT_DIV_CNT))begin Conv_Done <= 1'd1; Data <= Data_r; end else begin Conv_Done <= 1'd0; Data <= Data; end endmodule |