目录
3.1 Error-[SC-SYSCAN-OCOMP] Unsupported compiler
3.2 Error-[SC-SYSCAN-PERL-N] Cannot find perl5
以一个加法器(Adder)为例,展示第一个SystemC程序。
VCS自带了一系列的SystemC例程,位于<$VCS_HOME/doc/examples/systemc/>目录下。本文所述的加法器,其完整工程文件,位于上述目录下的<./vcs/simple/>目录:
[user@centos7 simple]$ ll
-rwxrwxr-x. 1 user user 1362 Oct 29 10:23 adder.h # Main Adder Program
-rwxrwxr-x. 1 user user 1531 Oct 29 10:23 adder.cpp # include adder.h
-rwxrwxr-x. 1 user user 2712 Oct 30 11:09 top.v # Testbench Top
-rwxrwxr-x. 1 user user 890 Oct 30 11:13 Makefile # Script for Running Sim
-rwxrwxr-x. 1 user user 1305 Oct 29 10:23 README
-rw-rw-r--. 1 user user 178 Oct 30 11:06 run.tcl # Script for Dump FSDB (Mannually Created)
...
1 代码文件介绍
1.1 adder.h文件
此文件,包含了一个SystemC形式的加法器的所有逻辑代码,包括顶层端口声明、内部逻辑实现:
SC_MODULE(adder)
{
public:
sc_in<sc_lv<32>> ina;
sc_in<sc_lv<32>> inb;
sc_out<sc_lv<32>> outx;
SC_CTOR(adder): ina("ina") , inb("inb"), outx("outx") {
SC_METHOD(adder_action);
sensitive << ina << inb;
}
// As inputs are triggered, drive the output.
void adder_action() {
sc_lv<32> val;
val = ina.read();
val = val.get_word(0) + inb.read().get_word(0);
outx.write( val );
}
};
1.2 adder.cpp文件
此文件,仅Include了上述addr.h文件,无其他逻辑代码:
#include "adder.h"
1.3 top.sv文件
此文件,作为整个仿真的顶层,完成对加法器的实例化,以及时钟信号、加法器输入激励的构造,仿真结束的控制:
`define W 31
module top();
parameter PERIOD = 20;
reg clock;
reg [`W:0] value1;
reg [`W:0] value2;
wire [`W:0] add_wire;
integer counter;
integer direction;
integer cycle;
// SystemC model
adder add1(value1, value2, add_wire);
initial begin
value1 = 32'b010; // starts at 2
value2 = 32'b000; // starts at 0
counter = 0;
direction = 1;
cycle = 0;
end
// clock generator
always begin
clock = 1'b0;
#PERIOD
forever begin
#(PERIOD/2) clock = 1'b1;
#(PERIOD/2) clock = 1'b0;
end
end
// stimulus generator
always @(posedge clock) begin
value1 <= counter+2;
value2 <= 32'b010; // stays at 2 after here.
if (direction == 1) // incrementing...
if (counter == 9) begin
counter = counter - 1;
direction = 0;
end
else
counter = counter + 1;
else // decrementing...
if (counter == 0) begin
counter = counter + 1;
direction = 1;
end
else
counter = counter - 1;
end
// display generator
always @(posedge clock) begin
$display("%d + %d = %d", value1, value2, add_wire);
// end after 100 cycles are executed
cycle = cycle + 1;
if (cycle == 20)
$finish;
end
endmodule
1.4 Makefile文件
此文件,调用VCS的相关命令,以VCS三步编译法,对上述SystemC、Verilog代码进行编译,并执行仿真。其中:
- syscan命令:对SystemC代码进行Analysis;
- vcs命令:对Verilog代码进行编译,并执行Elaboration;
此处,作者对Makefile文件进行了一些改造,包括:
- 声明CPP、GCC、CXX等变量,以显式地指定VCS所使用的cpp、gcc、g++命令的版本;同时,将syscan、vcs命令的-cc、-cpp选项的值,改为这些变量;
- 声明SYSTEMC_VER变量,以显式地指定VCS所使用的SystemC的版本;同时,为syscan、vcs命令传入-sysc=${SYSTEMC_VER}选项;
- 为syscan命令传入-cflags "-g"选项,为vcs命令传入-cflags "-g"选项、-debug_access+all选项;
- 为syscan、vcs命令传入-kdb选项,便于Verdi查看波形;
- 将simv改为./simv,解决“make: simv: Command not found”的问题;
- 为simv命令传入-ucli -ucli2Proc -do run.tcl选项,通过UCLI指定运行run.tcl文件的方式,来执行仿真。其中,run.tcl文件主要用于设置FSDB Dump的相关属性,以及开始仿真;
- 添加wave命令,能够调用Verdi来查看波形;
CPP := /usr/bin/cpp
GCC := /usr/bin/gcc
CXX := /usr/bin/g++
SYSTEMC_VER := 2.3.1
SYSTEMC_HOME := /usr/share/systemc-2.3.0
CLANG := /usr/bin/clang
all : comp run
clean :
\rm -fr csrc AN.DB ucli.key
\rm -fr simv* *.log DEFAULT.DB DVEfiles/ *.vpd
comp : clean
syscan -cc ${GCC} -cpp ${CXX} -cflags "-g" -kdb -sysc=${SYSTEMC_VER} adder.cpp:adder
vcs -cc ${GCC} -cpp ${CXX} -cflags "-g" -kdb -sysc=${SYSTEMC_VER} -debug_access+all -lca -sysc top.v -timescale=1ps/1ps -l comp.log
run :
./simv -ucli -ucli2Proc -do run.tcl -l run.log
wave :
verdi -ssf verilog_000.fsdb -lca &
1.5 run.tcl文件
此文件,为作者自行添加,主要用于设置FSDB Dump的相关属性,以及开始仿真:
set wave_type fsdb
# Auto switch dumpfile
fsdbAutoSwitchDumpfile 1000 "verilog.fsdb" 20
# Set dump cfg
fsdbDumpvars 0 +power top
# Start to run simulation till finished
run
2 运行仿真
2.1 运行Makefile脚本
在运行makefile脚本之前,务必确认Server上的VCS、Verdi工具的相关环境变量,已正确设置(涉及$VCS_HOME、$VERDI_HOME等相关变量)。
[user@centos7 simple]$ make comp run wave
2.2 仿真结果Log
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Oct 30 12:23 2022
ucli% set wave_type fsdb
fsdb
ucli% # Auto switch dumpfile
ucli% fsdbAutoSwitchDumpfile 1000 "verilog.fsdb" 20
*Verdi* Loading libsscore_vcs201809.so
*Verdi* : Loading SystemC dumping library libsscore_vcs201809_sc231_gcc483.so.
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
(C) 1996 - 2019 by Synopsys, Inc.
*Verdi* FSDB: The switch FSDB file size might not match the input size (1000MB) because of performance concerns.
*Verdi* FSDB: To have the FSDB file size match the input size (1000MB), set the FSDB_ENV_PRECISE_AUTOSWITCH environment, though the dumping performance might decrease.
*Verdi* : Enable automatic switching of the FSDB file.
*Verdi* : (Filename='verilog', Limit Size=1000MB, File Amount=20).
*Verdi* : Create FSDB file 'verilog_000.fsdb'
*Verdi* : Create the file 'verilog.log' to log the time range of each FSDB file.
*Verdi* : Create virtual FSDB file 'verilog.vf' to log each FSDB file.
ucli% # Set dump cfg
ucli% fsdbDumpvars 0 +power top
*Verdi* : Begin traversing the scope (top), layer (0).
*Verdi* : Enable +power and +force dumping.
*Verdi* : +power option is used in the design without power intent from UPF,
*Verdi* : no power information will be dumped
*Verdi* : End of traversing.
ucli% # Start to run simulation till finished
ucli% run
2 + 0 = 2
2 + 2 = 4
3 + 2 = 5
4 + 2 = 6
5 + 2 = 7
6 + 2 = 8
7 + 2 = 9
8 + 2 = 10
9 + 2 = 11
10 + 2 = 12
11 + 2 = 13
10 + 2 = 12
9 + 2 = 11
8 + 2 = 10
7 + 2 = 9
6 + 2 = 8
5 + 2 = 7
4 + 2 = 6
3 + 2 = 5
2 + 2 = 4
$finish called from file "top.v", line 92.
$finish at simulation time 410
V C S S i m u l a t i o n R e p o r t
Time: 410 ps
CPU Time: 1.270 seconds; Data structure size: 0.0Mb
Sun Oct 30 12:23:06 2022
2.3 仿真结果波形
3 问题记录
3.1 Error-[SC-SYSCAN-OCOMP] Unsupported compiler
这个问题,是因为Server上的g++工具的版本,不满足SystemC的要求所导致。解决的办法,如同Log信息中所示,使用-cpp、-cc选项,为syscan、vcs命令指定一个特定版本的gcc、g++工具。
另外,针对Linux OS的自带GCC版本更新缓慢,而某些软件又需要GCC特定版本或者高版本的问题,我们可通过添加devtoolset源安装GCC的多个特定版本,并且可以非常方便地在各个版本之间进行切换,详见 centos6使用devtoolset快速升级GCC版本4.8/5.2/8.3 。
3.2 Error-[SC-SYSCAN-PERL-N] Cannot find perl5
TODO