在聚合中使用切片
VHDL-2008允许您形成一个数组聚合，并将其分配到多个位置—全部集中在一个位置陈述
例如，如果in1定义为
std_logic_vector(3 downto 0) :
(my_reg1, my_reg2, enable, reset) <= in1;
This example assigns all four signals to the individual bits of in1 :
my_reg1 gets in1(3)
my_reg2 gets in1(2)
enable is in1(1)
reset is in1(0)
In addition, these signals can be assigned out of order, as shown in the following example:
(1=> enable, 0 => reset, 3 => my_reg1, 2 => my_reg2) <= in1;
Types
Unconstrained Element Types
Previously, in VHDL, types and subtypes had to be fully constrained in declaring the type. In
VHDL-2008, it is allowed to be unconstrained, and the constraining happens with the objects
that are of that type; consequently, types and subtypes are more versatile. For example:
subtype my_type is std_logic_vector;
signal my_reg1 : my_type (3 downto 0);
signal my_reg2 : my_type (4 downto 0);
In previous versions of VHDL, the preceding example was done with 2 subtypes. Now, in
VHDL-2008, this can be accomplished with one type. This can even be done for arrays, as shown
in the following example:
type my_type is array (natural range <>) of std_logic_vector;
signal : mytype(1 downto 0)(9 downto 0);
Using boolean_vector and integer_vector Array
Types
VHDL-2008 supports new predefined array types. Vivado supports boolean_vector and
integer_vector . These types are defined as follows:
type boolean_vector is array (natural range <>) of boolean
type integer_vector is array (natural range <>) of integer
混杂的
读取输出端口
在VHDL的早期版本中，将声明为out的信号用于除输出。因此，如果您想为输出分配一个值，并对其他逻辑使用相同的信号必须声明一个新信号，并使其驱动输出和其他逻辑，或者从输出类型切换到缓冲类型。
VHDL-2008允许您使用输出值，如以下示例所示：
entity test is port(
in1 : in std_logic;
clk : in std_logic;
out1, out2 : out std_logic);
end test;
And later in the architecture:
process(clk) begin
if clk'event an clk='1' then
out1 <= in1;
my_reg <= out1; -- THIS WOULD HAVE BEEN ILLEGAL in VHDL.
out2 <= my_reg;
end if;
end process;
端口映射中的表达式
VHDL-2008允许在实例化的端口映射中使用函数和分配。一种有用的方法是将信号从一种类型转换为另一种类型，如以下示例：
U0 : my_entity port map (clk => clk, in1 => to_integer(my_signal)...
在前面的例子中，实体my_entity有一个名为in1的端口，其类型为integer，但是在上层，信号mysignal的类型为stdlogicvector。以前在VHDL中，您必须创建一个integer类型的新信号，并执行实例化之外的转换，并将该新信号分配给端口映射。除了类型转换之外，还可以将逻辑放入端口映射中，如下所示实例
U0 : my_entity port map (clk => clk, enable => en1 and en2 ...
在这种情况下，较低电平具有使能信号。在顶层，enable与另外两个信号的AND。以前在VHDL中，这与前面的例子一样，需要一个新的信号和但是在VHDL-2008中可以在端口映射中实现实例化。
使用流程（全部）语句
在VHDL中当列出用于组合逻辑的过程语句的敏感度列表中的项目时，这取决于设计者来确保流程语句所读取的所有项目都已列出。如果如果错过了任何，则会出现警告消息，并在设计中推断出可能的锁存器。使用VHDL-2008，您可以使用process（all）语句来查找的所有输入处理并创建逻辑。
process(all) begin
enable <= en1 and en2;
end process;
Referencing Generics in Generic Lists
VHDL-2008 allows generics to reference other generics, as shown in the following example:
entity my_entity is generic (
gen1 : integer;
gen2 : std_logic_vector(gen1 - 1 downto 0));
In previous versions of VHDL, having the length of gen2 be controlled by gen1 was illegal.
Generics in Packages
VHDL-2008 supports putting a generic in a package and being able to override that generic when
the package is declared. For example:
package my_pack is
generic(
length : integer);
subtype my_type is std_logic_vector(length-1 downto 0);
end package my_pack;
This declares a subtype of std_logic_vector but does not specify the length. The calling VHDL file
specifies what the length should be when the package is instantiated:
library ieee;
use leee.std_logic_1164.all;
package my_pack1 is new work.my_pack generic map (length => 5);
package my_pack2 is new work.my_pack generic map (length => 3);
use work.my_pack1.all;
use work.my_pack2.all;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
clk : in std_logic;
in1 : in work.my_pack1.my_type;
in2 : in work.my_pack2.my_type;
out1 : out work.my_pack1.my_type;
out2 : out work.my_pack2.my_type);
end test;
This code uses the same package to declare two different subtypes and be able to use them.
Generic Types in Entities
VHDL-2008 supports undefined types in the generic statement for an entity. For example:
entity my_entity is
generic (type my_type);
port (in1 : in std_logic;
out1 : out my_type);
end entity my_entity;
This would declare an entity with an undetermined type, and the RTL that instantiates my_entity
would look like:
my_inst1 : entity work.my_entity(beh) generic map (my_type => std_logic)
port map ...
my_inst2 : entity work.my_entity(beh) generic map (my_type =>
std_logic_vector(3 downto 0)) port map ...
The previous code instantiates my_entity twice, but in one case, out1 is a bit, and in the other
case, out1 is a 4-bit vector.
Functions in Generics
In VHDL-2008, you can declare undefined functions inside of entities. For example
entity bottom is
generic (
function my_func (a,b : unsigned) return unsigned);
port ...
......
end entity bottom;
Later in the architecture of the entity:
process(clk) is
begin
if rising_edge(clk) then
y <= my_func(a,b);
end if;
end process;
This uses the my_func function, inside of the entity, but it still has not defined what this function
actually accomplishes. That is defined as when the bottom is instantiated in an upper-level RTL.
inst_bot1 : bottom
generic map (
my_func => my_func1 )
port map ...
这将VHDL文件或包文件中声明的函数my_func1与泛型函数my_func。只要my_func1有两个名为a和b的输入，它们都是无符号的，那么它就是能够工作。
函数返回值的宽松返回规则
在VHDL的早期版本中，函数的返回表达式需要与以下类型相同在函数中声明的函数返回类型。在VHDL-2008中，规则放宽到允许将返回表达式隐式转换为返回类型。例如
subtype my_type1 is std_logic_vector(9 downto 0);
subtype my_type2 is std_logic_vector(4 downto 0);
function my_function (a,b : my_type2) return my_type1 is
begin
return (a&b);
end function;
由于串联不是静态的，这将在VHDL中返回错误或警告；然而，它是VHDL-2008允许。
全局静态和局部静态表达式的扩展
在VHDL中，许多类型的地方的表达式都需要是静态的。例如，使用串联在与运算符或一起使用时不会返回静态值函数，该函数需要一个导致错误的静态值。VHDL-2008允许更多的表达式，比如级联以返回静态值，从而允许更大的灵活性。范围边界中的静态范围和整数表达式在VHDL中，可以通过使用另一个对象的范围来声明一个对象。例如
for I in my_signal'range...
这将要求my_signal的范围是固定的，但如果my_signal被声明为不受约束的类型，这将导致错误。VHDL-2008现在通过获取详细说明时的范围。
阻止注释
在VHDL中，每条有注释的行都需要注释“--”。在VHDL-2008中支持使用/*和*/行的注释块。
process(clk) begin
if clk'event and clk='1' then
/* this
is
a block
comment */
out1 <= in1;
end if;
end process;
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