Dri_TIM.c
#include "Dri_TIM.h"
void Dri_TIM4_Init()
{
RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
RCC->APB2ENR |= RCC_APB2ENR_IOPBEN;
GPIOB->CRH |= (GPIO_CRH_CNF8_1 | GPIO_CRH_MODE8);
GPIOB->CRH &= ~GPIO_CRH_CNF8_0;
GPIOB->CRH |= (GPIO_CRH_CNF9_1 | GPIO_CRH_MODE9);
GPIOB->CRH &= ~GPIO_CRH_CNF9_0;
TIM4->PSC = 1 - 1;
TIM4->ARR = 7200 - 1;
TIM4->CR1 &= ~TIM_CR1_DIR;
TIM4->CCR3 = 0;
TIM4->CCMR2 &= ~TIM_CCMR2_CC3S;
TIM4->CCMR2 |= TIM_CCMR2_OC3M_2;
TIM4->CCMR2 |= TIM_CCMR2_OC3M_1;
TIM4->CCMR2 &= ~TIM_CCMR2_OC3M_0;
TIM4->CCER |= TIM_CCER_CC3E;
TIM4->CCER &= ~TIM_CCER_CC3P;
TIM4->CCR4 = 0;
TIM4->CCMR2 &= ~TIM_CCMR2_CC4S;
TIM4->CCMR2 |= TIM_CCMR2_OC4M_2;
TIM4->CCMR2 |= TIM_CCMR2_OC4M_1;
TIM4->CCMR2 &= ~TIM_CCMR2_OC4M_0;
TIM4->CCER |= TIM_CCER_CC4E;
TIM4->CCER &= ~TIM_CCER_CC4P;
TIM4->CR1 |= TIM_CR1_CEN;
}
void Dri_TIM2_Init()
{
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
RCC->APB2ENR |= (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN|RCC_APB2ENR_AFIOEN);
AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;
AFIO->MAPR &= ~(AFIO_MAPR_SWJ_CFG_2 | AFIO_MAPR_SWJ_CFG_0);
# AFIO->MAPR |= AFIO_MAPR_TIM2_REMAP_FULLREMAP;
GPIOB->CRL &= ~GPIO_CRL_MODE3;
GPIOB->CRL &= ~GPIO_CRL_CNF3_1;
GPIOB->CRL |= GPIO_CRL_CNF3_0;
GPIOA->CRH &= ~GPIO_CRH_MODE15;
GPIOA->CRH &= ~GPIO_CRH_CNF15_1;
GPIOA->CRH |= GPIO_CRH_CNF15_0;
TIM2->PSC = 1 - 1;
TIM2->ARR = 0xFFFF;
TIM2 -> SMCR |= TIM_SMCR_SMS;
TIM2 -> SMCR &= ~TIM_SMCR_SMS_2;
TIM2 -> CCMR1 |= (TIM_CCMR1_CC1S_0|TIM_CCMR1_CC2S_0);
TIM2 -> CCMR1 &= ~(TIM_CCMR1_CC1S_1|TIM_CCMR1_CC2S_1);
TIM2 -> CCER &= ~(TIM_CCER_CC1P|TIM_CCER_CC2P);
TIM2 ->CR1 |= TIM_CR1_CEN;
}
void Dri_TIM3_Init()
{
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
RCC->APB2ENR |= (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN|RCC_APB2ENR_AFIOEN);
AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;
AFIO->MAPR &= ~(AFIO_MAPR_SWJ_CFG_2 | AFIO_MAPR_SWJ_CFG_0);
AFIO->MAPR |= AFIO_MAPR_TIM3_REMAP_1;
AFIO->MAPR &= ~AFIO_MAPR_TIM3_REMAP_0;
GPIOB->CRL &= ~GPIO_CRL_MODE4;
GPIOB->CRL &= ~GPIO_CRL_CNF4_1;
GPIOB->CRL |= GPIO_CRL_CNF4_0;
GPIOB->CRL &= ~GPIO_CRL_MODE5;
GPIOB->CRL &= ~GPIO_CRL_CNF5_1;
GPIOB->CRL |= GPIO_CRL_CNF5_0;
TIM3->PSC = 1 - 1;
TIM3->ARR = 0xFFFF;
TIM3 -> SMCR |= TIM_SMCR_SMS;
TIM3 -> SMCR &= ~TIM_SMCR_SMS_2;
TIM3 -> CCMR1 |= (TIM_CCMR1_CC1S_0|TIM_CCMR1_CC2S_0);
TIM3 -> CCMR1 &= ~(TIM_CCMR1_CC1S_1|TIM_CCMR1_CC2S_1);
TIM3 -> CCER &= ~(TIM_CCER_CC1P|TIM_CCER_CC2P);
TIM3 ->CR1 |= TIM_CR1_CEN;
}
Dri_TIM.h
#ifndef __DRI_TIM_H
#define __DRI_TIM_H
#include "stm32f10x.h"
void Dri_TIM4_Init();
void Dri_TIM2_Init();
void Dri_TIM3_Init();
#endif