牛客网刷题进阶挑战VL25——VL49

VL25 输入序列连续的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
 
reg 	[4:0] 	state;
reg		[4:0]	next_state;

parameter IDLE=5'd0,S1=5'd1,S2=5'd2,S3=5'd3,S4=5'd4,
S5=5'd5,S6=5'd6,S7=5'd7,S8=5'd8;

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		state<=IDLE;// reset
	end
	else  begin
		state<=next_state;
	end
end

always @(*) begin
	case(state)
	IDLE:begin
		if (a==1) begin
			next_state<=IDLE;
		end
		else begin
			next_state<=S1;
		end
	end
	S1:begin
		if (a==1) begin
			next_state<=S2;
		end
		else begin
			next_state<=S1;
		end
	end
	S2:begin
		if (a==1) begin
			next_state<=S3;
		end
		else begin
			next_state<=S1;
		end
	end
	S3:begin
		if (a==1) begin
			next_state<=S4;
		end
		else begin
			next_state<=S1;
		end
	end
	S4:begin
		if (a==0) begin
			next_state<=S5;
		end
		else begin
			next_state<= IDLE;
		end
	end
	S5:begin
		if (a==0) begin
			next_state<=S6;
		end
		else begin
			next_state<=S2;
		end
	end	
	S6:begin
		if (a==0) begin
			next_state<=S7;
		end
		else begin
			next_state<=S2;
		end
	end
	S7:begin
		if (a==1) begin
			next_state<=S8;
		end
		else begin
			next_state<=S1;
		end
	end
	S8:begin
		if (a==0) begin
			next_state<=S1;
		end
		else begin
			next_state<=IDLE;
		end
	end		
	default:
	next_state<=IDLE;	
	endcase
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		match<=0;// reset
		
	end
	else if (state==S8) begin
		match<=1;
	end
	else begin
		match<=0;
	end
end


endmodule

VL26 含无关项的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg 	[8:0]	a_tem;
wire	match_temp;

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		a_tem <= 0;// reset
	end
	else  begin
		a_tem <= {a_tem[7:0],a};
	end
end

assign match_temp = ((a_tem[8:6]==3'b011)&&(a_tem[2:0]==3'b110)) ;
  
always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		match <= 0;// reset
	end
	else  begin
		match<=match_temp;
	end
end
endmodule

VL27不重叠序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

parameter IDLE=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,FAIL=7;

reg [2:0] cnt;
reg	[2:0] state,next_state;

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		cnt<=0;// reset
	end
	else if (cnt=='d6) begin
		cnt<=1;
	end
	else begin
		cnt<=cnt+1'b1;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		state<=IDLE;// reset
		
	end
	else  begin
		state<=next_state;
	end
end

always @(*) begin
	case(state)
		IDLE:begin
			if (data==0&&cnt==0) begin
				next_state=s1;
			end
			else begin
				next_state=FAIL;
			end
		end
		s1:begin
			if (data==1) begin
				next_state=s2;
			end
			else begin
				next_state=FAIL;
			end
		end
		s2:begin
			if (data==1) begin
				next_state=s3;
			end
			else begin
				next_state=FAIL;
			end
		end
		s3:begin
			if (data==1) begin
				next_state=s4;
			end
			else begin
				next_state=FAIL;
			end
		end
		s4:begin
			if (data==0) begin
				next_state=s5;
			end
			else begin
				next_state=FAIL;
			end
		end
		s5:begin
			if (data==0) begin
				next_state=s6;
			end
			else begin
				next_state=FAIL;
			end
		end
		s6:begin
			if(data==0)begin
				next_state=s1;
			end
			else
				next_state=FAIL;
		end
		FAIL:begin
			next_state=(data==0&&cnt==6)?s1:FAIL;
		end
		default:next_state<=IDLE;
	endcase
end

always@(*)begin
	if (!rst_n) begin
		match=0;
		not_match=0;
	end
	else begin
		 match     = cnt==6&&state==s6;
         not_match = cnt==6&&state==FAIL;
	end
end

endmodule

VL28 输入序列不连续的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

parameter IDLE=0,s1=1,s2=2,s3=3,s4=4;
reg	[2:0]	state,next_state;

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		state<=IDLE;// reset
	end
	else begin
		state<=next_state;
	end
end

always @(*) begin
	case(state)
	IDLE:next_state=(data==0&&data_valid==1)?s1:IDLE;
	s1:next_state=(data==1&&data_valid==1)?s2:IDLE;
	s2:next_state=(data==1&&data_valid==1)?s3:IDLE;
	s3:next_state=(data==0&&data_valid==1)?s4:IDLE;
	s4:next_state=(data==0&&data_valid==1)?s1:IDLE;
	endcase
end

always@(*)begin
	match=(state==s4);
end

endmodule

VL29 信号发生器

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);
	reg  [4:0]    cnt_sequare; //方波   周期20
	reg  [4:0]    cnt_sawtooth;//锯齿波 周期21
	reg  [5:0]    cnt_triangle;//三角波 周期20
	reg           triangle_flag; //0代表下降 1 代表上升；
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			cnt_sequare<=5'b0;
		else if(wave_choise==2'd0)
			if(cnt_sequare<5'd19)
				cnt_sequare<=cnt_sequare+1'b1;
			else
				cnt_sequare<=5'b0;
		else
			cnt_sequare<=5'b0;
	end

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			triangle_flag<=1'b0;
		else if(wave_choise==2'd2)
			if(wave==5'd1)
				triangle_flag<=1'b1;
			else if(wave==5'd19)
				triangle_flag<=1'b0;
			else
				triangle_flag<=triangle_flag;
		else
			triangle_flag<=1'b0;
	end
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			wave<=5'd0;
		else case(wave_choise)
			2'd0 : wave <= (cnt_sequare == 9) ?20 : (cnt_sequare ==19) ? 0 :wave;
			2'd1 : wave <= (wave==20) ? 5'd0 : wave+1'b1;
			2'd2 : wave <= (triangle_flag==1'b0) ? wave-1'b1 : wave+1'b1;
			default :wave<=5'd0;
		endcase
	end
endmodule

VL30 数据串转并电路

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg	[2:0] cnt;
reg [5:0] temp;

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		cnt<=0;// reset
	end
	else if (valid_a&&ready_a)begin
		cnt<=(cnt==5)?'d0:(cnt+1'b1);
	end
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		temp<=0;// reset
	end
	else if (valid_a&&ready_a) begin
		temp<={data_a,temp[5:1]};
	end
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		data_b<=0;// reset
	end
	else if (cnt=='d5) begin
		data_b<={data_a,temp[5:1]};
	end
	else begin
		data_b<=data_b;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		valid_b<=0;// reset
	end
	else if (cnt=='d5) begin
		valid_b<=1;
	end
	else begin
		valid_b<=0;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		ready_a<=0;// reset
	end
	else  begin
		ready_a<=1;
	end
end






endmodule

VL31 数据累加输出

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);

reg	[1:0] cnt;

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		cnt<=0;// reset
	end
	else if (valid_a&&ready_a) begin
		cnt<=cnt+1'b1;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		data_out<=0;// reset
	end
	else if (valid_a&&ready_a&&cnt!=0) begin
		data_out<=data_out+data_in;
	end
	else if (valid_a&&ready_a&&cnt==0) begin
		data_out<=data_in;
	end
	else begin
		data_out<=data_out;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		valid_b<=0;// reset
	end
	else if (cnt==3&&valid_a&&ready_a) begin
		valid_b<=1;
	end
	else if(cnt==0&&valid_a&&ready_a) begin
		valid_b<=0;
	end
	else begin
		valid_b<=valid_b;
	end
end

assign ready_a = (!valid_b)|ready_b ;

endmodule

VL32 非整数倍数据位宽转换24to128

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);

reg [3:0]	cnt;
reg [127:0]	temp;

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		cnt<=0;// reset
	end
	else if (valid_in) begin
		cnt<=cnt+1'b1;
	end
	else begin
		cnt<=cnt;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		valid_out<=0;// reset
	end
	else if ((cnt==5||cnt==10||cnt==15)&&valid_in) begin
		valid_out<=1;
	end
	else begin
		valid_out<=0;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		temp<=0;// reset
	end
	else begin
		temp<=valid_in?{temp[103:0],data_in}:temp;
	end
end

always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            data_out <= 0;
        else if(cnt==5)
            data_out <= valid_in? {temp[119:0], data_in[23:16]}: data_out;
        else if(cnt==10)
            data_out <= valid_in? {temp[111:0], data_in[23: 8]}: data_out;
        else if(cnt==15)
            data_out <= valid_in? {temp[103:0], data_in[23: 0]}: data_out;
        else
            data_out <= data_out;
    end

endmodule

VL33 非整数倍数据位宽转换8to12

`timescale 1ns/1ns
 
module width_8to12(
    input                  clk      ,  
    input                 rst_n     ,
    input                     valid_in  ,
    input   [7:0]              data_in  ,
  
    output  reg            valid_out,
    output  reg [11:0]   data_out
);
 
reg [1:0] cnt;
reg [11:0]  data_lock;
 
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cnt<=0;// reset
    end
    else if (valid_in&&cnt<2) begin
        cnt<=cnt+1;
    end
    else if (valid_in&&cnt==2) begin
        cnt<=0;
    end
	else
		cnt<=cnt;
end
 
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        valid_out<=0;// reset
    end
    else if (cnt==1&&valid_in) begin
        valid_out<=1;
    end
    else if (cnt==2&&valid_in) begin
        valid_out<=1;
    end
	else
		valid_out<=0;
end
 
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        data_lock<=0;// reset
    end
    else if(valid_in) begin
        data_lock<=valid_in?{data_lock[3:0],data_in}:data_lock;
    end
end
 
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        data_out<=0;// reset
    end
    else if (cnt==1&&valid_in) begin
        data_out<={data_lock[7:0],data_in[7:4]};
    end
    else if (cnt==2&&valid_in) begin
        data_out<={data_lock[3:0],data_in};     
    end
end
 
 
endmodule

VL34 整数倍数据位宽转换8to16

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);

reg cnt;
reg [15:0]	data_lock;

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		cnt<=0;// reset
	end
	else if (valid_in) begin
		cnt<=cnt+1'b1;
	end
	else begin
		cnt<=cnt;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		data_lock<=0;	// reset
		
	end
	else if (valid_in) begin
		data_lock<={data_lock[7:0],data_in};
	end
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		data_out<=0;// reset
	end
	else if (valid_in&&cnt==1) begin
		data_out<={data_lock[7:0],data_in};
	end
	else begin
		data_out<=data_out;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		valid_out<=0;// reset
	end
	else if (cnt==1&&valid_in) begin
		valid_out<=1;
	end
	else begin
		valid_out<=0;
	end
end



endmodule

VL35 状态机-非重叠的序列检测

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5;
reg [2:0]	state,next_state;

always @(posedge clk or negedge rst) begin
	if (!rst) begin
		state<=s0;// reset
		
	end
	else  begin
		state<=next_state;
	end
end

always@(*)begin
	case(state)
	s0:begin
		if (data) begin
			next_state<=s1;
		end
		else begin
			next_state<=s0;
		end
	end
	s1:begin
		if (!data) begin
			next_state<=s2;
		end
		else begin
			next_state<=s1;
		end
	end
	s2:begin
		if (data) begin
			next_state<=s3;
		end
		else begin
			next_state<=s2;
		end
	end
	s3:begin
		if (data) begin
			next_state<=s4;
		end
		else begin
			next_state<=s3;
		end
	end
	s4:begin
		if (data) begin
			next_state<=s5;
		end
		else begin
			next_state<=s4;
		end
	end
	s5:begin
		if (data) begin
			next_state<=s1;
		end
		else begin
			next_state<=s0;
		end
	end
	endcase
end

always @(posedge clk or negedge rst) begin
	if (!rst) begin
		flag<=0;// reset
		
	end
	else if (next_state==s5) begin
		flag<=1;
	end
	else begin
		flag<=0;
	end
end

endmodule

VL36 状态机-重叠序列检测

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter s0=0,s1=1,s2=2,s3=3,s4=4;
reg [2:0] state,next_state;

always @(posedge clk or negedge rst) begin
	if (!rst) begin
		state<=s0;// reset
		
	end
	else  begin
		state<=next_state;
	end
end

always@(*)begin
	case(state)
	s0:begin
		if (data) begin
			next_state=s1;
		end
		else begin
			next_state=s0;
		end
	end
	s1:next_state=(data)?s1:s2;
	s2:next_state=data?s3:s0;
	s3:next_state=data?s4:s2;
	s4:next_state=data?s1:s2;
	default:next_state=s0;
	endcase
end

always @(posedge clk or negedge rst) begin
	if (!rst) begin
		flag<=0;// reset
		
	end
	else if (state==s4) begin
		flag<=1;
	end
	else begin
		flag<=0;
	end
end


//*************code***********//
endmodule

VL37 时钟分频（偶数）

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg cnt_2;
reg [1:0] cnt_4;
reg [2:0] cnt_8;

reg clk_out2_t;
reg clk_out4_t;
reg clk_out8_t;


always @(posedge clk_in or negedge rst) begin
	if (!rst) begin
		cnt_2<=0;// reset
	end
	else  begin
		cnt_2<=cnt_2+1'b1;
	end
end

always @(posedge clk_in or negedge rst) begin
	if (!rst) begin
		clk_out2_t<=0;// reset	
	end
	else if (cnt_2==1||cnt_2==0) begin
		clk_out2_t<=!clk_out2_t;
	end
end

always @(posedge clk_in or negedge rst) begin
	if (!rst) begin
		cnt_4<=0;// reset
	end
	else  begin
		cnt_4<=cnt_4+1'b1;
	end
end

always @(posedge clk_in or negedge rst) begin
	if (!rst) begin
		clk_out4_t<=0;// reset	
	end
	else if (cnt_4==0||cnt_4==2) begin
		clk_out4_t<=!clk_out4_t;
	end
end

always @(posedge clk_in or negedge rst) begin
	if (!rst) begin
		cnt_8<=0;// reset
	end
	else  begin
		cnt_8<=cnt_8+1'b1;
	end
end

always @(posedge clk_in or negedge rst) begin
	if (!rst) begin
		clk_out8_t<=0;// reset	
	end
	else if (cnt_8==4||cnt_8==0) begin
		clk_out8_t<=!clk_out8_t;
	end
end

assign clk_out2 = clk_out2_t;
assign clk_out4 = clk_out4_t;
assign clk_out8 = clk_out8_t;
//*************code***********//
endmodule

VL38 自动贩售机1

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
reg [3:0] cnt;
always @(posedge clk or negedge rst) begin
	if (!rst) begin
		cnt<=0;// reset
		out1<=0;
		out2<=0;
	end
	else  begin
		if (d1) begin
			cnt<=cnt+1;
		end
		else if (d2) begin
			cnt<=cnt+2;
		end
		else if (d3) begin
			cnt<=cnt+4;
		end
		else if (cnt>=3) begin
			out1<=1;
			out2<=cnt-3;
			cnt<=0;
		end
		else begin
			out1<=0;
			out2<=0;
		end

	end
end

//*************code***********//
endmodule

VL39 自动贩售机2

`timescale 1ns/1ns
//状态机写法
module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//

    parameter S0=0, S0_5=1, S1=2, S1_5=3, S2=4, S2_5=5, S3=6;
    reg[2:0] state, nstate;
    
    always@(posedge clk or negedge rst) begin
        if(~rst)
            state <= 0;
        else
            state <= nstate;
    end
    
    always@(*) begin
        case(state)
            S0     : nstate = d1? S0_5:
                              d2? S1:
                              nstate;
            S0_5   : nstate = d1? S1:
                              d2? S1_5:
                              nstate;
            S1     : nstate = d1? S1_5:
                              d2? S2:
                              nstate;
            S1_5   : nstate = ~sel? S0:
                              d1? S2:
                              d2? S2_5:
                              nstate;
            S2     : nstate = ~sel? S0:
                              d1? S2_5:
                              d2? S3:
                              nstate;
            default: nstate = S0;
        endcase
    end
    
    always@(*) begin
        if(~rst) begin
            {out1, out2, out3} = 3'b000;
        end
        else begin
            case(state)
                S0, S0_5, S1: {out1, out2, out3} = 0;
                S1_5        : {out1, out2, out3} = ~sel? 3'b100: 3'b000;
                S2          : {out1, out2, out3} = ~sel? 3'b101: 3'b000;
                S2_5        : {out1, out2, out3} = ~sel? 3'b101: 3'b010;
                S3          : {out1, out2, out3} = ~sel? 3'b101: 3'b011;
                default     : {out1, out2, out3} = 3'b000;
            endcase
        end
    end
//*************code***********//
endmodule

VL40 占空比50%的奇数分频

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg clk_out7_d1;
reg clk_out7_d2;
reg [2:0] cnt;
always @(posedge clk_in or negedge rst) begin
	if (!rst) begin
		cnt<=0;// reset
	end
	else if(cnt==4) begin
		cnt<=1;
	end
	else begin
		cnt<=cnt+1;
	end
end

always @(posedge clk_in or negedge rst) begin
	if (!rst) begin
		clk_out7_d1<=0;// reset
	end
	else if (cnt==4) begin
		clk_out7_d1<=!clk_out7_d1;
	end
end

always @(negedge clk_in or negedge rst) begin
	if (!rst) begin
		clk_out7_d2<=0;// reset
		
	end
	else if (cnt==4) begin
		clk_out7_d2<=!clk_out7_d2;
	end
end

assign clk_out7 =clk_out7_d1&&clk_out7_d2 ;


//*************code***********//
endmodule

VL42 无占空比要求的奇数分频

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//

reg [2:0] cnt;
reg clk_out_temp;

always @(posedge clk_in or negedge rst) begin
	if (!rst) begin
		cnt<=0;// reset
	end
	else if (cnt==4) begin
		cnt<=0;
	end
	else begin
		cnt<=cnt+1'b1;
	end
end

always @(posedge clk_in or negedge rst) begin
	if (!rst) begin
		clk_out_temp<=0;// reset
	end
	else if (cnt==0||cnt==2) begin
		clk_out_temp<=!clk_out_temp;
	end
end

assign clk_out5 = clk_out_temp;





//*************code***********//
endmodule

VL43 根据状态转移写状态机-三段式

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter s0=0,s1=1,s2=2,s3=3;
reg [1:0] state,next_state;

always @(posedge clk or negedge rst) begin
	if (!rst) begin
		state<=s0;// reset
	end
	else  begin
		state<=next_state;
	end
end

always@(*)begin
	case(state)
	s0:next_state=data?s1:s0;
	s1:next_state=data?s2:s1;
	s2:next_state=data?s3:s2;
	s3:next_state=data?s0:s3;
	default:next_state=s0;
	endcase
end

always @(posedge clk or negedge rst) begin
	if (!rst) begin
		flag<=0;// reset
	end
	else if (state==s3&&data==1) begin
		flag<=1;
	end
	else begin
		flag<=0;
	end
end



//*************code***********//
endmodule

VL44 根据状态转移写状态机-二段式

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//
parameter s0=0,s1=1,s2=2,s3=3,s4=4;
reg [2:0] state,next_state;

always @(posedge clk or negedge rst) begin
	if (!rst) begin
		state<=s0;// reset
	end
	else  begin
		state<=next_state;
	end
end

always@(*)begin
	case(state)
	s0:begin
		next_state=data?s1:s0;
		flag=0;
	end
	s1:begin
		next_state=data?s2:s1;
		flag=0;
	end
	s2:begin
		next_state=data?s3:s2;
		flag=0;		
	end
	s3:begin
		next_state=data?s4:s3;		
		flag=0;
	end
	s4:begin
		next_state=data?s1:s0;
		flag=1;
	end				
	endcase
end
//*************code***********//
endmodule

VL47格雷码计数器

`timescale 1ns/1ns

module gray_counter(
   input   clk,
   input   rst_n,

   output  reg [3:0] gray_out
);
    reg[4:0] count;
    reg rev;
    always@(posedge clk or negedge rst_n)
    if(!rst_n)
        count <= 5'b0;
    else
        count <= count + 1'b1;
    
    always@(*)
    if(!rst_n)
        gray_out = 4'b0;
    else
        gray_out = count[4:1] ^ (count[4:1] >> 1);
 

endmodule

VL48 多bitMUX同步器

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);

reg	[3:0] data_reg;
reg data_en_a,data_en_b0,data_en_b1;

always @(posedge clk_a or negedge arstn) begin
	if (!arstn) begin
		data_reg<=0;// reset
		
	end
	else  begin
		data_reg<=data_in;
	end
end

always @(posedge clk_a or negedge arstn) begin
	if (!arstn) begin
		data_en_a<=0;// reset
	end
	else  begin
		data_en_a<=data_en;
	end
end

always @(posedge clk_b or negedge brstn) begin
	if (!brstn) begin
		data_en_b0<=0;// reset
		data_en_b1<=0;
	end
	else  begin
		data_en_b0<=data_en_a;
		data_en_b1<=data_en_b0;
	end
end

always@(posedge clk_b or negedge brstn) begin
    if(~brstn)
        dataout <= 0;
    else
        dataout <= data_en_b1? data_reg: dataout;
end



endmodule

VL49 脉冲同步电路

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
    reg data_level, data_level1, data_level2, data_level3;
    
  	// 脉冲信号转电平信号
    always@(posedge clk_fast or negedge rst_n) begin
        if(~rst_n)
            data_level <= 0;
        else
            data_level <= data_in? ~data_level: data_level;
    end
    
  	// 电平信号打两拍再转为脉冲信号
    always@(posedge clk_slow or negedge rst_n) begin
        if(~rst_n) begin
            data_level1 <= 0;
            data_level2 <= 0;
            data_level3 <= 0;
        end
        else begin
            data_level1 <= data_level;
            data_level2 <= data_level1;
            data_level3 <= data_level2;
        end
    end
    assign dataout = data_level3^data_level2;
endmodule