Serial to Parallel 74HC595

Serial to Parallel HC595

以下数据节录自 TI http://www.ti.com SN74HC595 规格书。

Idle state:
Clk / SRCLK = idle low, rising edge, hold time ~ 500ns.
Latch / RCLK = idle low, high active, hold time ~ 500ns.
Wide Operating Voltage Range of 2 V to 6 V

Pin / Hardware:

sbit  hwHX595SDI        = 0x93;  // Serial Data,  595 Pin 14
sbit  hwHX595LATCH  = 0x95;  // Latch, CS,    595 Pin 12
sbit  hwHX595CLK       = 0x94;  // Serial Clock, 595 Pin 11
sbit  hwHX595nOE       = 0x95 Output Enable.  <Low active>

1. Pin 12 - RCLK = LATCH, .
   MUST-BE keep low after latched. Otherwise, shift register’s data may apply to output when shifting that results noising on output channels.
2. Pin 11 - SRCLK = Shifting Register clock.
3. Pin 14 - Serial Data Input = SDI.
4. Pin9 QH’ - Serail Data Out for next module = SDO
   QH’ 比 QH 提前半個相位